TuRTLe-Leaderboard / config /constants.py
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RESULTS_DIR = "results"
ICARUS_RESULTS = f"{RESULTS_DIR}/results_icarus.json"
VERILATOR_RESULTS = f"{RESULTS_DIR}/results_verilator.json"
ICARUS_AGG = f"{RESULTS_DIR}/aggregated_scores_icarus.csv"
VERILATOR_AGG = f"{RESULTS_DIR}/aggregated_scores_verilator.csv"
DISCARDED_MODELS = {
}
"""
"DeepSeek R1": "10/10/2025",
"QwenCoder 2.5 7B": "11/10/2025",
"RTLCoder Mistral": "14/10/2025"
"""
TASKS = ["Spec-to-RTL", "Code Completion", "Line Completion †"]
S2R_BENCHMARKS = ["VerilogEval S2R", "RTLLM"]
CC_BENCHMARKS = ["VerilogEval MC", "VeriGen"]
LC_BENCHMARKS = ["RTL-Repo"]
MODEL_TYPES = ["All", "General 🟒", "Coding πŸ”΅", "RTL-Specific πŸ”΄"]
TYPE_EMOJI = {"RTL-Specific": "πŸ”΄", "General": "🟒", "Coding": "πŸ”΅"}
NON_RTL_METRICS = ["Syntax (STX)", "Functionality (FNC)", "Synthesis (SYN)", "Power", "Performance", "Area"]
RTL_METRICS = ["Exact Matching (EM)"]
COLUMN_MAPPINGS = {
"Params": "Parameters (B)",
"Syntax (STX)": "Syntax",
"Functionality (FNC)": "Functionality",
"Synthesis (SYN)": "Synthesis",
"Post-Synthesis (PSQ)": "Post-Synthesis",
}
COLUMN_ORDER = [
"Type",
"Model",
"Parameters (B)",
"Syntax",
"Functionality",
"Synthesis",
"Post-Synthesis",
]
TYPE_COLORS = {"General": "green", "Coding": "yellow", "RTL-Specific": "blue"}
Y_AXIS_LIMITS = {
"Functionality (FNC)": [5, 90],
"Syntax (STX)": [20, 100],
"Synthesis (SYN)": [5, 90],
"Power": [0, 50],
"Performance": [0, 50],
"Area": [0, 50],
"Exact Matching (EM)": [0, 50],
}
SCATTER_PLOT_X_TICKS = {
"tickvals": [8, 14, 32, 72, 200, 700],
"ticktext": ["8", "14", "32", "72", "200", "700"],
}
DEFAULT_MAX_PARAMS = 700
DEFAULT_TASK = "Spec-to-RTL"
DEFAULT_BENCHMARK = "All"
DEFAULT_MODEL_TYPE = "All"
SIMULATORS = ["Icarus", "Verilator"]